Integrated circuits increasingly require very close spacing of interconnect lines and many now require multiple levels of metalization, as many as seven, to interconnect the various circuits on the device. Since closer spacing increases capacitance between adjacent lines, as the device geometries shrink and densities increase capacitance and cross talk between adjacent lines becomes more of a problem. Therefore, it becomes increasingly more desirable to use materials with lower dielectric constants to offset this trend and thereby lower capacitance between closely spaced interconnects.
Interconnect capacitance is a distributed quantity in the metalization, however, two components dominate: the line-to-substrate, or line-to-ground capacitance and line-to-line capacitance. For ultra large scale integration at 0.25 micron design rules and beyond, performance is dominated by interconnect RC delay, with line-to-line capacitance being the dominant contributor to total capacitance. For example, theoretical modeling has shown that when the width/spacing is scaled down below 0.3 micron, the interlayer capacitance is so small that total capacitance is dictated by the line-to-line capacitance, which constitutes more than 90% of the total interconnect capacitance. Therefore, a reduction of the line-to-line capacitance alone will provide a dramatic reduction in total capacitance.
The intermetal dielectric (IMD) of the prior art is typically SiO.sub.2 which has a dielectric constant of about 4.0. It would be desirable to replace this material with a material having a lower dielectric constant. As used herein, low dielectric constant or low-k means a material having a dielectric constant of lower than about 3.5 and preferably lower than 3 and most preferably about 2 or lower. Unfortunately, materials having a lower dielectric constant have characteristics that make them difficult to integrate into existing integrated circuit structures and processes. Many polymeric materials such as polysilsesquioxane, parylene, polyimide, benzocyclobutene and amorphous Teflon have lower dielectric constants (lower permittivities). Other preferred materials are Aerogel or Xerogel which are typically made from a gelation of tetraethoxysilane (TEOS) stock solution. Compared to SiO.sub.2, these preferred low-k materials typically have low mechanical strength, poor dimensional stability, poor temperature stability, high moisture absorption and permeation, poor adhesion, large thermal expansion coefficient and an unstable stress level. Because of these attributes, the use of polymer or other low dielectric materials as a stand alone replacement for SiO.sub.2 in integrated circuit processes or structures is very problematic.
An earlier application, by applicant herein, Ser. No. 60/013,866 (TI-21880) disclosed a method and structure for integrating HSQ and other low dielectric constant materials. This application discloses creating a multilayer dielectric stack of alternating layers of low-k materials and traditional dielectrics. The more fragile low-k material is ruggedized by a stabilizing layer inserted between layers of low-k films.
Another previous co-assigned application, Ser. No. 60/ (TI-19738) disclosed a method and structure for integrating HSQ into mesa isolation structures.